AltaVista Index Talk (Mike Burrows)

some notes:

  1. continuation design is good, avoid a lot of unused branchs.
  2. For some critical code piece, Choose instructions to dual-issue well, Fixed word structure allows prefetch, Avoid branch mispredictions.
  3. branch mispredications will suffer a lot of performance, but the question is that in x86 how to reduce the branch mispredication, I am very familiar with how to optimize the application in RISC, but not x86 micro-architecuture. Now I use the Vtune tools to get the performance results but don’t know how to reduce the branch mispredications. If you have some ideas, please tell me. thanks a lot.
  4. The interface for index stream readers(ISRs):  loc(),  next(), seek(X)
  5. constraint solve processing is very critical to index serve.
  6. Queries take about 100 cycles/query/MByte(AltaVista), 1.5G index size
  7. 30% inner loop, 15% constraint solver, 15% higher level seek code, 7% ranking code, 0.2% merging results, Miss ratios: 2% I-cache, 8% D-cache, 8% level-2 cache, 40% level-3 cache. It seems that the current ranking algorithm is more complex than the one in 2000.


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